ADVANCED MEMORY OPTIMIZATION TECHNIQUES FOR LOW-POWER EMBEDDED PROCESSORS

Le Monde En Tique

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Ouvrage 9781402058967 : ADVANCED MEMORY OPTIMIZATION TECHNIQUES FOR LOW-POWER EMBEDDED PROCESSORS
About this book
The design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the memory wall problem. Therefore, this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses.
The evaluation of the optimization techniques using real-life benchmarks for a single processor system, a multiprocessor system-on-chip (SoC) and for a digital signal processor system, reports significant reductions in the energy consumption and performance improvement of these systems. The book presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies. The final chapter covers optimization techniques for applications consisting of multiple processes found in most modern embedded devices.
Advanced Memory Optimization Techniques for Low Power Embedded Processors is designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem.
Table of contents
1. Introduction. 1.Design of Consumer Oriented Embedded Devices. 2.Contributions. 3.Outline.
2. Related Work. 1.Power and Energy Relationship. 2.Survey on Power and Energy Optimization Techniques.
3. Memory Aware Compilation and Simulation Framework. 1.Uni-Processor ARM. 2.Multi-Processor ARM. 3.M5 DSP.
4. Non-Overlayed Scratchpad Allocation Approaches for Main / Scratchpad Memory Hierarchy. 1.Introduction. 2.Motivation. 3.Related Work. 4.Problem Formulation and Analysis. 5.Non-Overlayed Scratchpad Allocation. 6.Experimental Results. 7.Summary.
5. Non-Overlayed Scratchpad Allocation Approaches for Main / Scratchpad + Cache Memory Hierarchy. 1.Introduction. 2.Related Work. 3.Motivating Example. 4.Problem Formulation and Analysis. 5.Cache Aware Scratchpad Allocation. 6.Experimental Results. 7.Summary.
6. Scratchpad Overlay Approaches for Main / Scratchpad Memory Hierarchy. 1.Introduction. 2.Motivating Example. 3.Related Work. 4.Problem Formulation and Analysis. 5.Scratchpad Overlay Approaches. 6.Experimental Results 7.Summary.
7. Data Partitioning and Loop Nest Splitting. 1.Introduction. 2.Related Work. 3.Problem Formulation and Analysis. 4.Data Partitioning. 5.Loop Nest Splitting. 6.Experimental Results. 7.Summary.
8. Scratchpad Sharing Strategies for Multiprocess Applications. 1.Introduction. 2.Motivating Example. 3.Related Work. 4.Preliminaries for Problem Formulation. 5.Non-Saving Approach. 6.Saving Approach. 7.Hybrid Approach. 8.Experimental Setup. 9.Experimental Results. 10. Summary.
9. Conclusions and Future Work. 1.Research Contributions. 2.Future Directions.
A. Theoretical Analysis for Scratchpad Sharing Strategies. 1. Formal Definitions. 2. Correctness Proof.
References.

Auteur : VERMA
Editeur : KLUWER
Nombre de pages : 170
Date de publication : 05 2007

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